In recent years, the semiconductor technical field has been said that miniaturization (scaling) comes to have its limitations, and an improvement in performance not relying on the miniaturization has been desired in the future. Examples of such a high-density packaging technology not relying on the miniaturization include a three-dimensional packaging technology in which stacking of semiconductor dies is performed. When semiconductor dies are packaged three-dimensionally, it has been conducted conventionally that a logic circuit whose power consumption is higher than that of a memory circuit is arranged in a semiconductor die being the lowermost layer, and on top of the semiconductor die, a low power semiconductor die such as a memory circuit is arranged.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2007-36104
[Patent Document 2] Japanese Laid-open Patent Publication No. 2008-251666
As scaling of semiconductor devices progresses, the cell size reduces, but it is difficult to reduce the wiring size to the cell size. Even in the three-dimensional packaging, as scaling is performed, the congestion of wirings increases. An increase in wiring congestion fails to secure a wiring region, and thus some wirings have to make a detour, resulting in that the device performance and the manufacturing yield are adversely affected. Further, a high-performance processor operates at a high frequency of several GHz, and thus the logic circuit is affected by crosstalk or the like caused by a clock signal in the semiconductor die. The effect of this crosstalk or the like on signal integrity is very large, and in order to prevent this effect, it is necessary to provide a shield wiring in the periphery of a clock wiring. Therefore, the wiring congestion further worsens to thus affect the device performance and the manufacturing yield.